Currently, an international standard such as IEEE 1588v2 has been established as a technique (see Patent Document 1) of performing clock synchronization using a packet network. In IEEE 1588v2, it is possible not only to synchronize the frequency of a clock but also to adjust a time or a phase of a clock. In IEEE 1588v2, a clock master device and a slave device to be synchronized with the master device are provided. Between the master device and the slave device, a delay time is measured by communication using a packet. Based on a measurement result of the delay time, synchronization of the frequency of a clock, time adjustment, and phase adjustment of a clock are implemented. For this reason, errors or fluctuations in the delay time affect the accuracy of clock reproduction of the slave device as is.
Most errors or fluctuations in the delay time are caused because a time until a clock synchronization packet is output after it is input to a packet transmission device is not constant. The fluctuations in the time occur due to control of quality of service (QoS) in a packet transmission device. Meanwhile, in IEEE 1588v2, a technique of correcting a delay time in a packet transmission device is defined. According to this technique, a packet transmission device conforming to IEEE 1588v2 can correct the errors in the delay time.